DS804 september 21, 2010 www.xilinx.com 1 product specification ? copyright 2010 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise and other designated brands included herein are tra demarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. introduction the axi external master connector (axi_ext_master_conn), lets you connect an axi master device outside of the embedded system module, using embedded module ports, to the slave interface of an axi interconnect ip with no intervening logic. the axi_ext_master_conn ip provides the port connection points necessary to represent the connectivity in the system, plus a set of parameters used to configure the slave interface of the connected axi interconnect module. features ? a set of ports comprising a standard axi slave interface, modeled as an i/o interface of the ip, which can be made external using xps tools. it provide the necessary signals that can be connected to an axi master device in the top-level system. ? one axi master bus-interface that connects to an axi interconnect in the embedded system. ? directly connects the external slave interface ports to the axi master bus-interface, and contains no logic or storage. t logicore? ip axi external master connector (v1.00.a) DS804 september 21, 2010 product specification logicore ip facts table core specifics core name axi_ext_master_conn supported device family (1) 1. for a complete listing of supported devices, see the release notes for this core. virtex ? -6, spartan ? -6, supported user interfaces axi4, axi4-lite tbd resources frequency configuration luts ffs dsp slices block rams max. freq. config1 0 0 0 0 n/a provided with core documentation product specification design files verilog, vhdl example design not provided test bench not provided constraints file not provided simulation model verilog, vhdl tested design tools design entry tools edk, xps simulation n/a synthesis tools xps support provided by xilinx, inc.
DS804 september 21, 2010 www.xilinx.com 2 product specification logicore? ip axi external master connector (v1.00.a) feature description the following figure illustrates the axi extern al master connection to an axi interconnect. i/o signals the following tables list the external slave signals and master i/o signals. external slave signals table 1 lists the external axi slave interface signal s that can connect to embedded system ports. x-ref target - figure 1 figure 1: system using axi external master connector ta bl e 1 : i/o slave signals signal name interface signal type description axi write address channel signals (aw) s_axi_awlen [7:0] aw i axi address write burst length. s_axi_awsize [2:0] aw i axi address write burst size. s_axi_awburst [1:0] aw i axi address write burst type. s_axi_awlock aw i axi write address lock signal. (1) s_axi_awcache [3:0] aw i axi write address cache control signal. s_axi_awprot [2:0] aw i axi write address protection signal. s_axi_awqos [3:0] aw i channel quality of service (qos). (1) s_axi_awuser [c_m_axi_awuser_width-1:0] aw i user-defined aw channel signals. s_axi_awvalid aw i axi write address valid. 1. advanced signal available for connection only when c_use_advanced_ports=1 . individ ua l axi port s m a de extern a l to sub - s y s tem interf a ce micro b l a ze edk sub - s y s tem axi_ext_m as ter_conn icaxi dcaxi s _axi m_axi memory controller axi_interconnect x12040
DS804 september 21, 2010 www.xilinx.com 3 product specification logicore? ip axi external master connector (v1.00.a) s_axi_awready aw o axi write address ready. axi write data channel signals (w) s_axi_wdata [c_m_axi_data_width-1:0] w i axi write data. s_axi_wstrb [c_m_axi_data_width/8-1:0] w i axi write data strobes. s_axi_wlast w i axi write data last signal. indicates the last transfer in a write burst. s_axi_wuser [c_m_axi_wuser_width-1:0] w i user-defined w channel signals. s_axi_wvalid w i axi write data valid. s_axi_wready w o axi write data ready. axi write response channel signals (b) s_axi_bid [c_m_axi_thread_id_width-1:0] b o axi write response id. (1) s_axi_bresp [1:0] b o axi write response code. s_axi_buser b o user defined b channel signals. s_axi_bvalid b o axi write response valid. s_axi_bready b i write response ready. axi read address channel signals (ar) s_axi_arid [c_m_axi_thread_id_width-1:0] ar i axi address read id. (1) s_axi_araddr [c_m_axi_addr_width-1:0] ar i axi read address. s_axi_arlen [7:0] ar i axi address read burst length. s_axi_arsize [2:0] ar i axi address read burst size. s_axi_arburst [1:0] ar i axi address read burst type. s_axi_arlock ar i axi read address lock signal. (1) s_axi_arcache [3:0] ar i axi read address cache control signal. s_axi_arprot [2:0] ar i axi r ead address protection signal. s_axi_arqos [3:0] ar i channel quality of service (qos). (1) s_axi_aruser [c_s_axi_aruser_width-1:0] ar i user-defined ar channel signals. s_axi_arvalid ar i axi read address valid. s_axi_arready ar o axi read address ready. axi read data channel signals (r) s_axi_rid [c_m_axi_thread_id_width-1:0] r o axi read data response id. (1) s_axi_rdata [c_s_axi_data_width-1:0] r o axi read data. s_axi_rresp [1:0] r o axi read response code. ta bl e 1 : i/o slave signals (cont?d) signal name interface signal type description 1. advanced signal available for connection only when c_use_advanced_ports=1 .
DS804 september 21, 2010 www.xilinx.com 4 product specification logicore? ip axi external master connector (v1.00.a) axi master interface signals table 2 lists the master interface signals that can connect to an axi interconnect ip in an embedded system. s_axi_rlast r o axi read data last signal. s_axi_ruser [c_s_axi_ruser_width-1:0] r o user-defined r channel signals. s_axi_rvalid r o axi read valid. s_axi_rready r i read ready. ta bl e 2 : axi master interface signals signal name interface signal type description axi write address channel signals (aw) m_axi_awid [c_m_axi_thread_id_width-1:0] aw o axi address write id. m_axi_awaddr [c_m_axi_addr_width-1:0] aw o axi write address. m_axi_awlen [7:0] aw o axi address write burst length. m_axi_awsize [2:0] aw o axi address write burst size. m_axi_awburst [1:0] aw o axi address write burst type. m_axi_awlock aw o axi write address lock signal. m_axi_awcache [3:0] aw o axi write address cache control signal. m_axi_awprot [2:0] aw o axi write address protection signal. m_axi_awqos [3:0] aw o channel quality of service (qos). m_axi_awuser [c_m_axi_awuser_width-1:0] aw o user-defined aw channel signals. m_axi_awvalid aw o axi write address valid. m_axi_awready aw i axi write address ready. axi write data channel signals (w) m_axi_wdata [c_m_axi_data_width-1:0] w o axi write data. m_axi_wstrb [c_m_axi_data_width/8-1:0] w o axi write data strobes. m_axi_wlast w o axi write data last signal. indicates the last transfer in a write burst. m_axi_wuser [c_m_axi_wuser_width-1:0] w o user-defined w channel signals. m_axi_wvalid w o axi write data valid. m_axi_wready w i axi write data ready. ta bl e 1 : i/o slave signals (cont?d) signal name interface signal type description 1. advanced signal available for connection only when c_use_advanced_ports=1 .
DS804 september 21, 2010 www.xilinx.com 5 product specification logicore? ip axi external master connector (v1.00.a) axi write response channel signals (b) m_axi_bid [c_m_axi_thread_id_width-1:0] b i axi write response id. m_axi_bresp [1:0] b i axi write response code. m_axi_buser b i user-defined b channel signals. m_axi_bvalid b o axi write response valid. m_axi_bready b i write response ready. axi read address channel signals (ar) m_axi_arid [c_s_axi_id_width-1:0] ar o axi address read id. m_axi_araddr [c_s_axi_addr_width-1:0] ar o axi read address. m_axi_arlen [7:0] ar o axi address read burst length. m_axi_arsize [2:0] ar o axi address read burst size. m_axi_arburst [1:0] ar o axi address read burst type. m_axi_arlock ar o axi read address lock signal. m_axi_arcache [3:0] ar o axi read address cache control signal. m_axi_arprot [2:0] ar o axi read address protection signal. m_axi_arqos [3:0] ar o ar channel quality of service (qos). m_axi_aruser [c_s_axi_aruser_width-1:0] ar i user-defined ar channel signals. m_axi_arvalid ar o axi read address valid. m_axi_arready ar i axi read address ready. axi read data channel signals (r) m_axi_rid [c_s_axi_id_width-1:0] r i axi read data response id. m_axi_rdata [c_s_axi_data_width-1:0] r i axi read data. m_axi_rresp [1:0] r i axi read response code. m_axi_rlast r i axi read data last signal. m_axi_ruser [c_s_axi_ruser_width-1:0] r i user-defined r channel signals. m_axi_rvalid r i axi read valid. m_axi_rready r o read ready. ta bl e 2 : axi master interface signals (cont?d) signal name interface signal type description
DS804 september 21, 2010 www.xilinx.com 6 product specification logicore? ip axi external master connector (v1.00.a) global i/o signals table 3 lists global signals of the ip. parameters table 4 lists the user-visible parameters. in addition to the pa rameters listed in this table, there are also inferred parameters for the m_axi interface in the edk tools. th rough the design, these inferred parameters control the behavior of the axi interconnect. for a co mplete list of the interconnect setting s related to the axi interface, see the axi interconnect ip data sheet (ds768). ta bl e 3 : global i/o signals signal name interface signal type init status description global signals aclk global i axi bus clock. aresetn global i axi active-low reset. ta bl e 4 : external master parameters parameter name default value allowable values description c_use_advanced_ports 0 0, 1 controls whether the less-common (advanced) axi signals are included in the external slave interface. c_m_axi_protocol axi4 string (axi3, axi4, axi4lite axi protocol used by the connected external master device. c_m_axi_addr_width 32 constant (32) width of addr signals (both s and m interfaces). c_m_axi_data_width 32 integer (32, 64, 128, 256) specifies the width of the wdata and rdata signals used by the connected external master device (applies to both s and m interfaces). c_m_axi_supports_read 1 0,1 specifies whether the connected external master device performs reads. c_m_axi_supports_write 1 0,1 specifies whether the connected external master device performs writes. c_m_axi_supports_threads 0 0,1 specifies whether the connected external master device produces any id signals (has reordering depth > 1). c_m_axi_thread_id_width 1 1-16 specifies the number of id bits produced by the connected external master device. c_m_axi_supports_narrow_burst 1 0,1 specifies whether the connected external master device produces ?narrow bursts? (transfer size less than data width for any multi-beat bursts). c_m_axi_supports_user_signals 0 0,1 specifies whether the connected external master device has any user signals on any axi channels. c_m_axi_awuser_width 1 integer (1-2147483647 specifies the number of awuser bits on the connected external master device. c_m_axi_buser_width 1 integer (1-2147483647 specifies the number of buser bits on the connected external master device.
DS804 september 21, 2010 www.xilinx.com 7 product specification logicore? ip axi external master connector (v1.00.a) support xilinx provides technical support for this logicore product when used as described in the product documentation. xilinx cannot guarantee ti ming, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized beyo nd that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . revision history the following table shows the revision history for this document: notice of disclaimer xilinx is providing this product documentation, hereinafter ?inf ormation,? to you ?as is? with no warranty of any kind, express or implied. xilinx makes no representation that the information, or any particular implementation thereof, is free from any claims of infringement. you are responsible for obtaining any rights you may require for any implementation based on the information. all specifications are subject to change without notice. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the information or any implementation based thereon, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. ex cept as stated herein, none of the information may be copied, reproduced, distributed, republished, downloaded, displ ayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or ot herwise, without the prior written consent of xilinx. c_m_axi_aruser_width 1 integer (1-2147483647 specifies the number of aruser bits on the connected external master device. c_m_axi_wuser_width 1 integer (1-2147483647 specifies the number of wuser bits on the connected external master device. c_m_axi_ruser_width 1 integer (1-2147483647 specifies the number of ruser bits on the connected external master device. date version description of revisions 09/21/2010 1.00 initial xilinx release. ta bl e 4 : external master parameters (cont?d) parameter name default value allowable values description
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